1. Field of the Invention
The present invention relates to display units, and more specifically to a low cost method and apparatus for scanning an image within a narrow horizontal line frequency range irrespective of the horizontal frequency at which the image is received.
2. Related Art
Display units are often used to receive and display image frames contained in a display signal. As used in the present application, display units include both analog display units (typically based on cathode ray tube (CRT) technology) and digital display units (typically based on flat panels). As is well known, the image frames are represented by pixel data elements encoded within display data portion of the display signal.
Display signals are generally characterized by frame rate and horizontal line frequency. The frame rate refers to the number of image frames encoded per second in the display signal. The horizontal line frequency refers to the number of horizontal lines encoded per second in the display signal. In general, a higher frame rate usually leads to better display quality due to correspondingly higher refresh rate. A high horizontal line frequency could be the result of a high frame rate and/or high resolution (number of lines in a frame) in the encoded image frames. In general, different display modes are specified according to corresponding standards, which further specify the frame rate and the horizontal line frequencies among other characteristics.
Display units are often designed to operate in conjunction with display signals of different display modes. Some of the display units automatically (i.e., without manual intervention) detect the specific display mode based on examination of a received display signal, and display the encoded images base on the detected display mode. Such monitors are often referred to as multi-scan display units in the relevant arts.
One problem with the display units which can operate with different display mode is that the overall cost of manufacturing the display units may be high. At least in the case of CRT display units, the high costs may be the result of the need to employ sophisticated deflection circuits (e.g., coils or yokes) which need to move the electronic beam to point from one end of the display screen to the other (horizontally and/or vertically) during the corresponding non-display time. The deflection circuits operating in the horizontal direction may be particularly costly as the retrace time in the horizontal direction may be particularly short. The high costs may be undesirable in many environments, particularly in the consumer markets.
Accordingly, specifications such as Generalized Timing Formula (GTF) developed by VESA allow a display unit to be implemented to operate with one or a very few display modes. According to the GTF, a display unit may indicate to the graphics source (generating the display signal) the specific display timing parameters (such as refresh rate and horizontal line frequency), and the graphics source generates a display signal consistent with the indicated parameters. As a result, a display unit may be implemented to operate with one or a limited numbers of display timing parameters, and thus the cost to manufacture the display unit may be minimized.
Even though the display units based on GTF type solutions may be produced cost effectively, the display units may not be adequate for operation in some situations. For example, a graphics source may not be implemented to support such (e.g., GTF compatible) solutions. Even if a graphics source is implemented to be GTF compliant, the compliance feature may not be always available. For example, a computer system implemented based on Windows 95 software (available from Microsoft Corporation) may not have the GTF compliant feature enabled when the system operates in xe2x80x98safe modexe2x80x99.
A prior system may use a frame buffer in such situations to receive images at one rate (xe2x80x9cframe ratexe2x80x9d) and to generate images for scanning at another rate (xe2x80x9cscan ratexe2x80x9d). The scan rate may be chosen such that the horizontal scanning frequencies falls within a desired frequency range. The scanning frequencies may be determined, for example, based on GTF. For further details on GTF, the reader is referred to a document entitled, xe2x80x9cGTF Standard, Version 1.1xe2x80x9d, available from Video Electronics Standards Association (VESA), and is incorporated in its entirety herewith. Due to the frame rate conversions possible with frame buffers, display units may be implemented with relatively inexpensive deflection circuits.
However, frame buffers add additional cost to the implementation of the overall display units, and may thus be undesirable. Accordingly, what is needed is a cost-effective approach which enables display units to display images within a narrow horizontal frequency range irrespective of the horizontal frequency at which a image is received.
The present invention enables a display unit to be implemented to scan images within a narrow horizontal frequency range irrespective of the frequencies at which the image frames are encoded in a received display signal. An apparatus scales the image frames in at least a vertical direction such that the number of lines in the scaled image times the frame rate at which the images are encoded in the display signal falls within the horizontal frequency range for which the display unit is designed for.
The scaled images are used to scan a display screen contained within the display unit. The images may be scanned at the same rate (xe2x80x9cframe ratexe2x80x9d) as the rate at which images are encoded in the display signal. As a result, the scaling operation may be implemented without using frame buffer memory type components. In addition, as the display screen is scanned within a narrow scanning frequency range, the cost to implement the scan circuitry and display screen may also be minimized.
Another aspect of the present invention allows an apparatus to be implemented to operate with both analog display signals and digital display signal. An interface circuit may contain an analog to digital converter (ADC) to sample the display data portion of the analog display signal to generate pixel data elements representing the encoded image frames. As is well known, analog display signal contain synchronization signals accompanying the display data portion. The interface circuit may also contain a digital receiver to recover the pixel data elements and synchronization signals encoded in a digital display signal.
A first multiplexor may be provided to select pixel data elements generated by one of the ADC and the digital receiver depending on whether the display unit is presently receiving analog display signal or the digital display signal. A second multiplexor may similarly select the synchronization signals from the two display signal types.
A line measurement circuit may examine the synchronization signals selected by the second multiplexor to determine the input horizontal frequency at which the lines are encoded in the display signal. The input horizontal frequency may be determined by other approaches also. For example, the display data portion of a display signal may be examined to determine the input horizontal frequency. A control circuit may then determine the number of lines to be contained in the scaled image. A scaler may scale the image consistent with the determination of the control circuit.
The control circuit may generate the synchronization signals corresponding to the scaled images. A third multiplexor may select either the scaled image or the image frame under the control of the control circuit. A fourth multiplexor may select the synchronization signals related to the display signal or the signals generated by the control circuit under the control of the control circuit. Thus, the outputs of the third and fourth multiplexors contain the data and signals for scanning the display screen.
As the horizontal lines represented by the outputs of the third and fourth multiplexors are always encoded with a frequency which falls in a pre-specified horizontal scanning range, the cost to implement the screen interfaces may be minimized. For example, relatively inexpensive horizontal deflection circuits may be employed. In addition, as the scaling may also be performed without using frame buffers, the overall cost of display units may also be minimized.
Further features and advantages of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.